Neural Networks: Neuromorphic Computing
List of Publications
- N. Karmokar, R. Harjani, and S.S. Sapatnekar, in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2023), pp. 1–2. Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays
- A.K. Sharma, M. Madhusudan, S.M. Burns, S. Yaldiz, P. Mukherjee, R. Harjani, and S.S. Sapatnekar, in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (2021), pp. 1–9. Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits
- B.R. Zink, Y. Lv, M. Zabihi, H. Cilasun, S.S. Sapatnekar, U.R. Karpuzcu, M.D. Riedel, and J.-P. Wang, “A Stochastic Computing Scheme of Embedding Random Bit Generation and Processing in Computational Random Access Memory (SC-CRAM),” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 9(1), 29–37 (2023).
- H. Cılasun, S. Resch, Z.I. Chowdhury, E. Olson, M. Zabihi, Z. Zhao, T. Peterson, K.K. Parhi, J.-P. Wang, S.S. Sapatnekar, and U.R. Karpuzcu, “Spiking Neural Networks in Spintronic Computational RAM,” ACM Trans. Archit. Code Optim. 18(4), 59:1-59:21 (2021). Spiking Neural Networks in Spintronic Computational RAM
- H. Cılasun, S. Resch, Z.I. Chowdhury, M. Zabihi, Y. Lv, B. Zink, J.-P. Wang, S.S. Sapatnekar, and U.R. Karpuzcu, “Error Detection and Correction for Processing in Memory (PiM),” (2022).
- H. Cılasun, S. Resch, Z.I. Chowdhury, M. Zabihi, Z. Zhao, T. Peterson, J.-P. Wang, S.S. Sapatnekar, and U.R. Karpuzcu, in 2021 International Symposium on Secure and Private Execution Environment Design (SEED) (2021), pp. 70–75. Seeds of SEED: H-CRAM: In-memory Homomorphic Search Accelerator using Spintronic Computational RAM
- H. Esmaeilzadeh, S. Ghodrati, A.B. Kahng, J. Kyung Kim, S. Kinzer, S. Kundu, R. Mahapatra, S.D. Manasi, S.S. Sapatnekar, Z. Wang, and Z. Zeng, in 2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD) (2022), pp. 119–126. Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms
- H. Esmaeilzadeh, S. Ghodrati, J. Gu, S. Guo, A.B. Kahng, J.K. Kim, S. Kinzer, R. Mahapatra, S.D. Manasi, E. Mascarenhas, S.S. Sapatnekar, R. Varadarajan, Z. Wang, H. Xu, B.R. Yatham, and Z. Zeng, in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (2021), pp. 1–7. Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems
- H. Lo, W. Moy, H. Yu, S. Sapatnekar, and C.H. Kim, A 48-Node All-to-All Connected Coupled Ring Oscillator Ising Solver Chip (In Review, 2023).
- J. Liu, S. Su, M. Madhusudan, M. Hassanpourghadi, S. Saunders, Q. Zhang, R. Rasul, Y. Li, J. Hu, A.K. Sharma, S.S. Sapatnekar, R. Harjani, A. Levi, S. Gupta, and M.S.-W. Chen, in 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD) (2021), pp. 1–9. From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning
- K. Kunal, T. Dhar, M. Madhusudan, J. Poojary, A.K. Sharma, W. Xu, S.M. Burns, J. Hu, R. Harjani, and S.S. Sapatnekar, “GNN-based Hierarchical Annotation for Analog Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1 (2023).
- K.M. Barijough, L. Huang, I.-H. Hou, S.S. Sapatnekar, J. Hu, and A. Gerstlauer, in Approximate Computing Techniques: From Component- to Application-Level, edited by A. Bosio, D. Ménard, and O. Sentieys (Springer International Publishing, Cham, 2022), pp. 287–322. Exploiting Approximations in Real-Time Scheduling
- M. Zabihi, S. Resch, H. Cılasun, Z.I. Chowdhury, Z. Zhao, U.R. Karpuzcu, J.-P. Wang, and S.S. Sapatnekar, “Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator,” (2021).
- M.A.A. Shohel, V.A. Chhabria, and S.S. Sapatnekar, in 2021 58th ACM/IEEE Design Automation Conference (DAC) (2021), pp. 913–918. A New, Computationally Efficient “Blech Criterion” for Immortality in General Interconnects
- N. Karmokar, A.K. Sharma, J. Poojary, M. Madhusudan, R. Harjani, and S.S. Sapatnekar, in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2022), pp. 166–171. Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays
- N. Karmokar, M. Madhusudan, A.K. Sharma, R. Harjani, M.P.-H. Lin, and S.S. Sapatnekar, in 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) (2022), pp. 114–121. Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead
- R. S, M. Madhusudan, A.K. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S.M. Burns, and S.S. Sapatnekar, in Proceedings of the 2022 International Symposium on Physical Design (Association for Computing Machinery, New York, NY, USA, 2022), pp. 159–166. Analog/Mixed-Signal Layout Optimization using Optimal Well Taps
- R.S. Gopalakrishnan, M. Madhusudan, A.K. Sharma, J. Poojary, S. Yaldiz, R. Harjani, S.M. Burns, and S.S. Sapatnekar, “A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts,” ACM Trans. Des. Autom. Electron. Syst., (2023).
- S. Kamineni, A. Sharma, R. Harjani, S.S. Sapatnekar, and B.H. Calhoun, in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2023), pp. 1–6. AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells
- S. Mondal, S.D. Manasi, K. Kunal, R. S, and S.S. Sapatnekar, in Proceedings of the 59th ACM/IEEE Design Automation Conference (Association for Computing Machinery, New York, NY, USA, 2022), pp. 565–570. GNNIE: GNN inference engine with load-balancing and graph-specific caching
- S. Mondal, S.D. Manasi, K. Kunal, R. S., Z. Zeng, and S.S. Sapatnekar, “A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, with Efficient Load Balancing and Graph-Specific Caching,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1–1 (2022).
- S. Resch, H. Cilasun, Z. Chowdhury, M. Zabihi, Z. Zhao, J.-P. Wang, S. Sapatnekar, and U.R. Karpuzcu, in Proceedings of the 50th Annual International Symposium on Computer Architecture (Association for Computing Machinery, New York, NY, USA, 2023), pp. 1–13. On Endurance of Processing in (Nonvolatile) Memory
- S. Resch, S.K. Khatamifard, Z.I. Chowdhury, M. Zabihi, Z. Zhao, H. Cilasun, J.-P. Wang, S.S. Sapatnekar, and U.R. Karpuzcu, “Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions,” ACM Trans. Embed. Comput. Syst. 21(5), 57:1-57:36 (2022).
- S. Resch, Z.I. Chowdhury, H. Cilasun, M. Zabihi, Z. Zhao, J.-P. Wang, S. Sapatnekar, and U.R. Karpuzcu, “Towards Homomorphic Inference Beyond the Edge,” (2021).
- S.M. Burns, H. Chen, T. Dhar, R. Harjani, J. Hu, N. Karmokar, K. Kunal, Y. Li, Y. Lin, M. Liu, M. Madhusudan, P. Mukherjee, D.Z. Pan, J. Poojary, S. Ramprasath, S.S. Sapatnekar, A.K. Sharma, W. Xu, S. Yaldiz, and K. Zhu, in Machine Learning Applications in Electronic Design Automation, edited by H. Ren and J. Hu (Springer International Publishing, Cham, 2022), pp. 505–544. Machine Learning for Analog Layout
- S.S. Sapatnekar, in 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (2022), pp. 1188–1188. EDAML 2022 Invited Speaker 7: Analog and Digital Circuit and Layout Optimization using Machine Learning
- S.S. Sapatnekar, in Proceedings of the 2023 International Symposium on Physical Design (Association for Computing Machinery, New York, NY, USA, 2023), pp. 101–102. The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues
- T. Dhar, R. S, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S.S. Sapatnekar, in 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2022), pp. 148–153. A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement
- V.A. Chhabria, C.C. Sudarshan, S. Vrudhula, and S.S. Sapatnekar, “Towards Sustainable Computing: Assessing the Carbon Footprint of Heterogeneous Systems,” (2023).
- V.A. Chhabria, W. Jiang, A.B. Kahng, and S.S. Sapatnekar, in 2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD) (2022), pp. 7–14. From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction
- W. Moy, I. Ahmed, P. Chiu, J. Moy, S.S. Sapatnekar, and C.H. Kim, “A 1,968-node coupled ring oscillator circuit for combinatorial optimization problem solving,” Nat Electron 5(5), 310–317 (2022).
- Y. Li, Y. Lin, M. Madhusudan, A. Sharma, S. Sapatnekar, R. Harjani, and J. Hu, “Performance-driven Wire Sizing for Analog Integrated Circuits,” ACM Trans. Des. Autom. Electron. Syst. 28(2), 19:1-19:23 (2022).
- Z. Chowdhury, S.K. Khatamifard, S. Resch, H. Cilasun, Z. Zhao, M. Zabihi, M. Razaviyayn, J.-P. Wang, S. Sapatnekar, and U.R. Karpuzcu, “CRAM-Seq: Accelerating RNA-Seq Abundance Quantification using Computational RAM,” IEEE Transactions on Emerging Topics in Computing, 1–1 (2022).
- Z. Zeng, and S.S. Sapatnekar, in 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2023), pp. 1–6. Energy-efficient Hardware Acceleration of Shallow Machine Learning Applications